We are pleased to introduce TSMC 3DFabric™, our comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. 3DFabric™ complements our advanced semiconductor technologies to unleash our customer's innovations.
Packaging technologies were once considered just backend processes, almost an inconvenience. Times have changed. Computing workloads have evolved more over the past decade than perhaps the previous four decades. Cloud computing, big data analytics, artificial intelligence (AI), neural network training, AI inferencing, mobile computing on advanced smartphones and even self-driving cars are all pushing the computing envelope.
Modern workloads have brought packaging technologies to the forefront for innovation and they are critical to a product's performance, function and cost. These modern workloads have pushed the product design to embrace a more holistic approach for optimization at the system level. 3DFabric™ offers our customers the freedom and advantage to design their products more holistically as a system of mini-chips that offers key advantages versus designing a larger monolithic die.
TSMC's 3DFabric™ consists of both frontend and backend technologies. Our frontend technologies, or TSMC-SoIC™ (System on Integrated Chips), use the precision and methodologies of our leading edge silicon fabs needed for 3D silicon stacking. TSMC also has multiple dedicated backend fabs that assemble and test silicon dies, including 3D stacked dies, and processes them into packaged devices. TSMC 3DFabric's backend technologies include the CoWoS® and InFO family of packaging technologies.
All diagrams, animations and videos are for demonstrative and illustrative purposes only
TSMC's 3DFabric offers our customers the ultimate flexibility in product design, brings packaging technologies to the forefront for innovation, and are critical to a product's performance, function and cost:
Time-to-Market: Customers can reuse technology blocks that do not change frequently or do not scale well to develop "chiplets" which allow for faster innovation and shorten the time-to-market
Performance and Efficiency: 3DFabric allows the integration of high density interconnected chips into a packaged module delivering improved bandwidth, latency, and power efficiency
Form Factor: Integrate varied logic, memory, or specialty chips with SOCs to deliver smaller form factors for various applications.
Cost: Customers can reuse blocks, such as analog IO, RF, and those that do not change frequently nor scale well, on more mature and lower cost semiconductor technologies. Customers can focus logic designs that scale well on TSMC’s most advanced semiconductor technologies