TSMC-SoIC^®

TSMC-SoIC^® services include the custom manufacturing of semiconductors, memory chips, wafers, integrated circuits, product research, custom design and testing for new product development, along with technology consultation services for electrical and electronic products, semiconductors, semiconductor systems, semiconductor cell libraries, wafers, and integrated circuits.

What is TSMC-SoIC^®?

TSMC-SoIC^® is a key technology pillar that advances heterogeneous chiplets integration. Such integration reduces size and increases performance. TSMC-SoIC^® features ultra-high-density-vertical stacking for high performance, low power, and minimum resistance-inductance-capacitance (RLC).

Key TSMC-SoIC^® features:

1. Heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies.

   (a) System-on-Chip (SoC) before chip partition; (b), (c), (d) Variant TSMC-SoIC^® partitioned chiplets and re-integration schemes

   
2. Exceptional scalability

   With an innovative bonding scheme, TSMC-SoIC^® technology enables the strong bonding pitch scalability for chip Input/Output (I/O) to realize high density die-to-die interconnects. The bond pitch starts from the sub-10 µm rule. A short die-to-die connection creates a smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption compared to current state-of-the-art packaging solutions.

   
3. Holistic 3D System Integration

   TSMC-SoIC^® technology integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip, with a smaller footprint and thinner profile that can be holistically integrated into advanced Wafer-Level-System-Integration (WLSI), aka Chip on Wafer on Substrate (CoWoS^®) or InFO). From the outside, the integrated chip looks like an ordinary SoC. But on the inside, it is embedded with heterogeneously integrated functionalities.