CoWoS®

CoWoS® platform provides best-in-breed performance and highest integration density for high performance computing applications. This wafer level system integration platform offers wide range of interposer sizes, number of HBM cubes, and package sizes. It can enable larger than 2X-reticle size (or ~1,700mm2) interposer integrating leading SoC chips with more than four HBM2/HBM2E cubes.

CoWoS-R is a member of CoWoS advanced packaging family leveraging InFO technology to utilize RDL interposer and to serve the interconnect between chiplets, especially in HBM(high bandwidth memory) and SoC heterogeneous integration. RDL interposer is comprised of polymer and copper traces, and it is relatively mechanically flexible. Such flexibility enhances the C4 joint integrity, and allows the new package can scale up its size to meet more complex functional demands.

CoWoS<sup>®</sup>-R

The key features of CoWoS-R technology include:

  1. The RDL interposer consists of up to 6L Cu layers for routing with min. of 4um pitch(2um line width/spacing).

  2. The RDL interconnect offers good signal and power integrity performance with lower RC value of the routing line to achieve a high transmission data rate. The coplanar GSGSG and interlayer ground shielding with six RDL interconnections offer superior electrical performance.

  3. RDL layer and C4/UF layers provide good buffer effect due to the CTE mismatch between SoC and the corresponding substrate. The strain energy density is greatly reduced in C4 bump.

    CoWoS<sup>®</sup>-R

CoWoS®-L, as one of the chip-last packages in CoWoS® platform, combining the merits of CoWoS®-S and InFO technologies to provide the most flexible integration using interposer with LSI (Local Silicon Interconnect) chip for die-to-die interconnect and RDL layers for power and signal delivery. The offering starts from 1.5X-reticle interposer size with 1x SoC + 4x HBM cubes and will move forward to expand the envelope to larger sizes for integrating more chips.

The key features of CoWoS®-L service include:

  1. LSI chips for high routing density die-to-die interconnect through multiple layers of sub-micron Cu lines. The LSI chips can feature variety of connection architectures (e.g. SoC to SoC, SoC to chiplet, SoC to HBM… etc) within each product, and can also be used repeatedly for multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS®-S.
  2. Molding-based interposer with wide pitch of RDL layers on both front-side and back-side and TIV (Through Interposer Via) for signal and power delivery provides low loss of high frequency signal in high-speed transmission.
  3. Capability of integrating additional elements, e.g. stand-alone IPD (Integrated Passive Device), right underneath the SoC die to support its signal communication with better PI/SI.
CoWoS<sup>®</sup>-L
The Chronicle of CoWoS
  • 2020
    • News Release
      2020/09/09
      Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
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      2020/03/03
      TSMC and Broadcom Enhance the CoWoS Platform with World’s First 2X Reticle Size Interposer
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  • 2019
    • Production Milestone
      More than 60 product tape-outs are in production or in development as of Aug. 2019
    • Customer Product
      Industry 1st 7nm GPU w/ deep learning accelerator
      • 1TB/s in BW
      • 4 HBM2
      • 1X reticle interposer
      AI training accelerator w/ 1.2TB/s in BW
      • N16+
      • 4 HBM2
      • 1.5X reticle interposer
  • 2018
    • Customer Product
      Fujitsu A64FX
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      Build your 56G Enterprise Networking ASICs with MediaTek
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  • 2017
    • Customer Product
      Broadcom Announces Industry's First Silicon-Proven 7nm IP for ASICs in Deep Learning and Networking Applications
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      NEC "Aurora" Vector Engine vector processor
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      Nvidia TESLA GV100
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    • Industry Publication
      IEEE Transaction on electronics devices 2017
      Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
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      IEDM 2017
      Advanced Heterogeneous Integration Technology Trend for Cloud and Edge
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  • 2016
    • Customer Product
      Nvidia TESLA GP100
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      Industry's first ASIC based AI accelerator from learning only to learning+inference
    • Industry Publication
      SEMICON Taiwan 2016
      Interposer Technology: Past, Now, and Future
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      SEMICON Taiwan 2016
      WLSI Extends Si Processing and Supports Moore's Law
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  • 2015
  • 2014
    • Customer Product
      HiSilicon Hi1616
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    • Industry Publication
      IEDM 2014
      A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration
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      IEDM 2014
      Wafer Level System Integration for SiP
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      CICC 2014
      New System-in-Package (SiP) Integration technologies
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  • 2013
    • Industry Publication
      VLSI 2013
      Manufacturability Optimization and Design Validation Studies for FPGA-Based, 3D Integrated Circuits
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      IITC 2013
      Innovative Wafer-based Interconnect Enabling System Integration and Semiconductor Paradigm Shifts
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      ECTC 2013
      Reliability Evaluation of a CoWoS-enabled 3D IC Package
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  • 2012
    • Customer Product
      Xilinx 7V2000T/7V580T
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    • Industry Publication
      VLSI 2012
      An ultra-thin interposer utilizing 3D TSV technology
      LEARN MORE
  • 2011
    • Industry Publication
      ECTC 2011
      Advanced Reliability Study of TSV Interposers and Interconnects for the 28nm Technology FPGA
      LEARN MORE

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