整合型扇出 (InFO) 封裝技術

台積公司推出的整合型扇出(Integrated Fan-Out, InFO)技術是一個創新的晶圓級系統整合技術平台,具有高密度多層線路重佈層(Redistribution Layer, RDL)以及晶圓穿透導孔(Through InFO Vias, TIVs),可實現高密度互連與卓越性能,,適用於多種應用領域,包括移動裝置與高效能運算。InFO技術平台提供針對特定應用進行最佳化的2.5D與3D封裝方案。

台積的整合型扇出層疊封裝(Integrated Fan-Out Package on Package, InFO-PoP)技術是業界首款3D晶圓級扇出封裝,具有高密度多層線路重佈層(RDL)與TIVs,可用於整合行動應用處理器與動態隨機存取記憶體(Dynamic Random-Access Memory, DRAM)封裝堆疊。與覆晶晶片封裝(Flip Chip Package-on-Package)相比,因為InFO-PoP不需要有機基板或C4凸塊設計,因此具備更優異的電氣和熱性能,同時封裝厚度更薄。

InFO_PoP

台積公司的整合型扇出暨封裝基板(Integrated Fan-Out on Substrate, InFO-oS)技術運用整合型扇出(InFO)技術,具備更高密度的多層線路重佈層(RDL)線寬/間距,可整合多個先進邏輯晶片。預期此晶片技術將廣泛應用於多種下一代產品的晶片組封裝設計中。

InFO_oS
The Chronicle of InFO
  • 2021
    • News Release
      2021/08/31
      GUC Announces Industry Highest Bandwidth and Power Efficient Die-to-Die (GLink 2.0) Total Solution
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  • 2020
    • News Release
      2020/11/17
      GUC Die-to-Die (D2D) Total Solution Opening the New Era of Flagship SoC
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  • 2019
    • Production Milestone
      More than 20 product tape-outs are in production or in development as of Aug. 2019
      TSMC has been shipping InFO in high volume since 2016
    • Customer Product
      N16 Network SoC
      • L/S < 2/2 µm
      • 1.5X reticle
    • Industry Publication
      ECTC 2019
      3D-MiM (MUST-in-MUST) Technology for Advanced System Integration
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      ECTC 2019
      Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications
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  • 2018
    • Customer Product
      N16 Network SoC
      • L/S < 2/2 µm
      • 1X reticle
      N7 Mobile SoC
      • L/S < 10/10 µm
      • PoP height < 1 mm
      N7 Wearable SoC
      • L/S < 10/10 µm
      • PoP height < 0.9 mm
    • Industry Publication
      ECTC 2018
      A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO Packaging
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      ECTC 2018
      High Performance, High Density RDL for Advanced Packaging
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      ECTC 2018
      InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration
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  • 2017
    • Production Milestone
      National Industrial Innovation Award
    • Customer Product
      N10 Mobile SoC
      • L/S < 10/10 µm
      • PoP height < 1 mm
    • Industry Publication
      IEDM 2017
      Advanced heterogeneous integration technology trend for cloud and edge
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      IRPS 2017
      CPI advancement in integrated fan-out (InFO) technology
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      ECTC 2017
      High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL
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  • 2016
    • Customer Product
      N16 Mobile SoC
      • L/S < 10/10 µm
      • PoP height < 1 mm
    • Industry Publication
      IEDM 2016
      Ultra-low-resistance 3D InFO inductors for integrated voltage regulator applications
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      ECTC 2016
      Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications
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      ECTC 2016
      InFO (Wafer Level Integrated Fan-Out) Technology
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      ECTC 2016
      Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications
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  • 2015
    • Industry Publication
      IEDM 2015
      High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology
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      IEEE 2015 International 3D Systems Integration Conference
      Power Saving and Noise Reduction of 28nm CMOS RF SystemIntegration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology
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  • 2013
    • Industry Publication
      IEDM 2013
      Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications
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      VLSI 2013
      High-Performance Inductors for Integrated Fan-Out Wafer Level Packaging (InFO-WLP)
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  • 2012
    • Industry Publication
      IEDM 2012
      High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration
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