InFO is an innovative wafer level system integration technology platform, featuring a high-density redistribution layer (RDL) and Through InFO Vias (TI) for high-density interconnect and performance in a variety of applications, including mobile and high-performance computing. The InFO platform offers 2.5D and 3D options optimized for specific applications.
InFO-PoP, the industry’s first 3D wafer-level fan-out package, features a high density RDL and TIVs to integrate mobile application processors with dynamic random access memory (DRAM). InFO-PoP has better electrical and thermal performance, and a thinner profile than flip chip package-on-package, because it has no organic substrate or C4 bump.
InFO-oS leverages Integrated Fan-Out (InFO) technology and features a higher density 2/2µm re-distribution interconnection (RDL) line width/space to integrate multiple advanced logic chiplets for 5G networking applications. It enables hybrid pad pitches on system-on-a-chip (SoC) with a minimum 36µm Input/Output (I/O) pitch, a minimum 130µm C4 copper bump pitch and a 2.5X reticle size InFO on 110x110 mm substrates. More chiplet packaging adoption is expected in a variety of next generation products.
