A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration
A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (Vcc) of 1.8V, and a leakage current (ILK) below 1 fA/µm2 under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/µm2, respectively, with their corresponding ILK below 0.48, 0.19 and 0.09 fAmp/µm2. Process reliability related defect density (D0) of the interposer HK-MiM is as low as 0.095% cm-2 as judged by a 10 years lifetime breakdown voltage (Vbd) criterion at Vcc=3.2V. This low D0 ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm2 within the Si interposer. Moreover, the Vbd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., ILK & Vbd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.
https://ieeexplore.ieee.org/document/7047119