Ultra-Low-Resistance 3D InFO Inductors for Integrated Voltage Regulator Applications
Authors: C.-L. Chen, Y.-C. Hsu, J.-S. Hsieh, C.-H. Tsai, V. C. Y. Chang, A. Roth, E. Soenen, C.-T. Wang, and Douglas Yu
A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 x 2.2 x 0.15 mm3. It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mΩ. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.
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