TSMC’s world-leading CoWoS® advanced 2.5D packaging technology provides the essential foundation for high-performance computing (HPC) and artificial intelligence (AI) products. By integrating multiple SoCs and high-bandwidth memory stacks, CoWoS® empowers products with high-performance compute and memory bandwidth. CoWoS®-S can accommodate an interposer up to 3.3X-reticle size (or ~2700mm2). CoWoS®-L or CoWoS®-R are recommended for larger than 3.3X-reticle interposer sizes. A variety of interconnect options provide integration flexibility to meet performance target.
Since entering volume production in 2012, the CoWoS® platform has continued to evolve, offering a growing number of options. With the advent of generative AI in late 2022, market demand for CoWoS® solutions has become even greater.
To support next-generation products such as HPC, AI, and mobile applications, TSMC continues to expand its advanced packaging capacity, helping customers accelerate innovation to meet rapidly changing market challenges.
TSMC’s CoWoS®-S solution provides best-in-class package technology for ultra-high performance computing applications. Wafer-level system integration provides high-density interconnects and embedded deep trench capacitors over a large silicon interposer area to accommodate various functional top dies, including logic chiplets, with high-bandwidth memory (HBM) cubes stacked over it. CoWoS® has been in production since 2012, with its silicon interposer size reaching up to 3.3X-reticle.
CoWoS®-R advanced packaging service achieves heterogeneous integration by using a redistribution layer (RDL) interposer as the interconnect between System-on-Chip (SoC) and/or high-bandwidth memory (HBM), having been in volume production since 2023. An RDL interposer is comprised of polymer and copper traces and is relatively flexible. This enhances C4 joint integrity and allows the package to scale to meet very complex functional demands.
Key CoWoS®-R features include:
- An RDL interposer for routing, with a minimum 4μm pitch (i.e., 2μm line width/spacing).
- An RDL interconnect offers good signal and power integrity with a lower RC value routing line to achieve a high data transmission rate. The co-planar Ground-Signal-Ground-Signal-Ground (GSGSG) and interlayer ground shielding with RDL interconnections offer superior electrical performance.
- RDL layer and C4/underfill (UF) layers provide an excellent buffer thanks to the coefficient of thermal expansion (CTE) mismatch between an SoC and the corresponding substrate. The strain energy density is greatly reduced in C4 bump area.
CoWoS®-L advanced packaging service enables larger high-performance computing (HPC) products by combining Chip on Wafer on Substrate with RDL-based interposer, higher density embedded local silicon interconnect (LSI), eDTC, and the integration of diverse embedded chips.
TSMC’s first CoWoS®-L at 3.5X-reticle size has been in volume production since 2024. To meet the escalating demand for higher package performance and artificial intelligence (AI) computing power, CoWoS®-L continues scaling the interposer size to integrate more silicon and memory in CoWoS®.
CoWoS®-L features include:
- LSI chips for a high routing density die-to-die interconnect through multiple layers of sub-micron copper lines. LSI chips can feature a variety of connection architectures, e.g., System-on-Chip (SoC)-to-SoC, SoC-to-chiplet, SoC-to-high-bandwidth memory (HBM), within each product, and can be used repeatedly in multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS®-S.
- A molding-based interposer with a wide pitch of RDL layers on the front-side and back-side that delivers signal and power provides a low loss of high frequency signals during high-speed transmission.
- The ability to integrate additional elements, such as stand-alone eDTCs underneath the SoC die to improve power management.
