TSMC’s Chip on Wafer on Substrate with Silicon Interposer (CoWoS®-S) provides best-in-class package technology for ultra-high performance computing applications, such as artificial intelligence (AI) and supercomputing. Wafer-level system integration provides high-density interconnects and deep trench capacitors over a large silicon interposer area to accommodate various functional top die, including logic chiplets, with high-bandwidth memory (HBM) cubes stacked over it. CoWoS®-S can accommodate an interposer up to 3.3X-reticle size (or ~2700mm2). CoWoS®-L or CoWoS®-R are recommended for larger than 3.3X-reticle interposer sizes. A variety of interconnect options provide integration flexibility to meet performance target.
Chip on Wafer on Substrate with Redistribution Layer Interposer (CoWoS®-R) technology service achieves heterogeneous integration by using a redistribution layer (RDL) interposer as the interconnect between System on Chip (SoC) and/or high-bandwidth memory (HBM). An RDL interposer is comprised of polymer and copper traces and is relatively flexible. This enhances C4 joint integrity and allows the package to scale to meet very complex functional demands.
Key CoWoS®-R features include:
- An RDL interposer for routing, with a minimum 4μm pitch (2μm line width/spacing).
- An RDL interconnect offers good signal and power integrity with a lower RC value routing line to achieve a high data transmission rate. The co-planar Ground-Signal-Ground-Signal-Ground (GSGSG) and interlayer ground shielding with RDL interconnections offer superior electrical performance.
- RDL layer and C4/underfill (UF) layers provide an excellent buffer thanks to the coefficient of thermal expansion (CTE) mismatch between an SoC and the corresponding substrate. The strain energy density is greatly reduced in C4 bump area.
CoWoS®-L technology service, combining Chip on Wafer on Substrate with RDL-based interposer and embedded local silicon interconnect (LSI), improves product design flexibility by integrating a variety of embedded chips. LSI with higher routing density and embedded deep trench capacitor (eDTC) enables larger-sized HPC products.
CoWoS®-L features include:
- LSI chips for a high routing density die-to-die interconnect through multiple layers of sub-micron copper lines. LSI chips can feature a variety of connection architectures, e.g., System on Chip (SoC)-to-SoC, SoC-to-chiplet, SoC-to-high-bandwidth memory (HBM), within each product, and can be used repeatedly in multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS®-S
- A molding-based interposer with a wide pitch of RDL layers on the front-side and back-side that delivers signal and power provides a low loss of high frequency signals during high-speed transmission
- The ability to integrate additional elements, such as stand-alone eDTCs underneath the SoC die to improve power management
