TSMC-SoIC^®

TSMC-SoIC^® is an innovative wafer-level 3D IC chip stacking platform.

TSMC-SoIC^® manufacturing service includes custom manufacturing of semiconductors, memory chips, wafers, integrated circuits, product research, custom design and testing for new product development, along with technology consultation services for electrical and electronic products, semiconductors, semiconductor systems, semiconductor cell libraries, wafers, and integrated circuits.

SoIC integrated chips can be subsquently assembled by using conventional packages or new TSMC 3DFabric^® technology services, such as CoWoS^® or TSMC-SoW™, for next-generation high-performance computing (HPC), artificial intelligence (AI), and mobile applications. Several ongoing developments will allow the SoIC family to unleash more innovations, including the SoIC Gen-2 process that enables advanced SoC (N2 and beyond) compatibility and compact universal photonics engine (COUPE) to enable Si photonic solution. TSMC will continue to pursue SoIC technological improvements and co-optimize with the Company’s advanced silicon technologies for further gains in transistor density, system power, performance, and area (PPA), and cost.

Key TSMC-SoIC^® features:

1. Exceptional Heterogeneous integration (HI)

   Integrating known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies.

   (a) System-on-Chip (SoC) before chip partition; (b), (c), (d) Variant TSMC-SoIC^® partitioned chiplets and re-integration schemes

   
2. Exceptional scalability

   With an innovative bonding scheme, TSMC-SoIC^® technology service enables bond pitch scalability for chip input/output (I/O) to realize high density die-to-die interconnects. The bond pitch starts from the sub-10µm rule. This technology provides high-density interconnect chiplet architectures for HPC products; its 3nm chip stacking technology successfully entered volume production in 2025. A short die-to-die connection creates a smaller form factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption compared to current state-of-the-art packaging solutions.

3. Holistic 3D System Integration

   TSMC-SoIC^® technology service integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip. With a smaller footprint and thinner profile, this chip can be holistically integrated into CoWoS^® and InFO. From the outside, the integrated chip looks like an ordinary SoC. But on the inside, it is embedded with heterogeneously integrated functionalities.