CoWoS^®

CoWoS-R is a member of CoWoS advanced packaging family leveraging InFO technology to utilize RDL interposer and to serve the interconnect between chiplets, especially in HBM(high bandwidth memory) and SoC heterogeneous integration. RDL interposer is comprised of polymer and copper traces, and it is relatively mechanically flexible. Such flexibility enhances the C4 joint integrity, and allows the new package can scale up its size to meet more complex functional demands.

The key features of CoWoS-R technology include:

1. The RDL interposer consists of up to 6L Cu layers for routing with min. of 4um pitch(2um line width/spacing).

2. The RDL interconnect offers good signal and power integrity performance with lower RC value of the routing line to achieve a high transmission data rate. The coplanar GSGSG and interlayer ground shielding with six RDL interconnections offer superior electrical performance.

3. RDL layer and C4/UF layers provide good buffer effect due to the CTE mismatch between SoC and the corresponding substrate. The strain energy density is greatly reduced in C4 bump.

   

CoWoS^®-L, as one of the chip-last packages in CoWoS^® platform, combining the merits of CoWoS^®-S and InFO technologies to provide the most flexible integration using interposer with LSI (Local Silicon Interconnect) chip for die-to-die interconnect and RDL layers for power and signal delivery. The offering starts from 1.5X-reticle interposer size with 1x SoC + 4x HBM cubes and will move forward to expand the envelope to larger sizes for integrating more chips.

The key features of CoWoS^®-L service include:

1. LSI chips for high routing density die-to-die interconnect through multiple layers of sub-micron Cu lines. The LSI chips can feature variety of connection architectures (e.g. SoC to SoC, SoC to chiplet, SoC to HBM… etc) within each product, and can also be used repeatedly for multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS^®-S.
2. Molding-based interposer with wide pitch of RDL layers on both front-side and back-side and TIV (Through Interposer Via) for signal and power delivery provides low loss of high frequency signal in high-speed transmission.
3. Capability of integrating additional elements, e.g. stand-alone IPD (Integrated Passive Device), right underneath the SoC die to support its signal communication with better PI/SI.