The CoWoS®-S (Chip on Wafer on Substrate with silicon interposer) platform provides best-in-class package technology for ultra-high performance computing applications, such as artificial intelligence (AI) and super-computing. This wafer level system integration platform offers high density interconnects and deep trench capacitors over a large silicon interposer area to accommodate various functional top die/dice, including logic chiplets, with High Bandwidth Memory (HBM) cubes stacked over it. Currently, an interposer up to 3.3X-reticle size (or ~2700mm2) is ready for production. The CoWoS®-L and CoWoS®-R platform are recommended for larger than 3.3X-reticle interposer sizes. Different interconnect options provide more flexibility integration to meet performance target.
CoWoS®-R (Chip on Wafer on Substrate with silicon interposer with fan-out RDL interposer) is a member of CoWoS® advanced packaging family that leverages a redistribution layer (RDL) interposer as the interconnect between System on Chip (SoC) and/or high bandwidth memory (HBM) to achieve heterogeneous integration. An RDL interposer is comprised of polymer and copper traces and is relatively flexible. This enhances C4 joint integrity and allows the package to scale its size to meet very complex functional demands.
Key CoWoS®-R features include:
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An RDL interposer of up to 6 copper layers for routing with a minimum 4μm pitch (2μm line width/spacing).
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The RDL interconnect offers good signal and power integrity with a lower RC value routing line to achieve a high data transmission rate. The co-planar Ground-Signal-Ground-Signal-Ground (GSGSG) and interlayer ground shielding with six RDL interconnections offers superior electrical performance.
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RDL layer and C4/underfill (UF) layers provide an excellent buffer thanks to the coefficient of thermal expansion (CTE) mismatch between an SoC and the corresponding substrate. The strain energy density is greatly reduced in C4 bump area.
CoWoS®-L is one of the chip-last packages on the CoWoS® (Chip on Wafer on Substrate) platform. It combines the merits of CoWoS®-S and InFO (Integrated Fan-Out) technologies to provide the most flexible integration using an interposer with a Local Silicon Interconnect (LSI) chip for die-to-die interconnect and RDL layers for power and signal delivery.
Key CoWoS®-L features include:
- LSI chips for a high routing density die-to-die interconnect through multiple layers of sub-micron copper lines. LSI chips can feature of a variety of connection architectures, e.g., System on Chip (SoC)-to-SoC, SoC-to-chiplet, SoC-to-High Bandwidth Memory, within each product, and can be used repeatedly in multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS®-S.
- A molding-based interposer with a wide pitch of RDL layers on the front-side, back-side and Through InFO Via (TIV) that delivers signal and power provides a low loss of high frequency signals during high-speed transmission.
- The ability to integrate additional elements, such as stand-alone embedded Deep Trench Capacitors, underneath the SoC die to improve power management.
