TSMC-SoIC™ platform is a key technology pillar to advance the field of heterogeneous chiplets integration with reduced size, increased performance. It features ultra-high-density-vertical stacking for high performance, low power, and min RLC (resistance-inductance-capacitance). TSMC-SoIC service platform integrates active and passive chips into a new integrated-SoC system, which is electrically identical to native SoC, to achieve better form factor and performance.
The key features of TSMC-SoIC service platform include:
Enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies.
(a) SoC before chip partition; (b), (c), (d) Variant partitioned chiplets and re-integrated schemes enabled by TSMC-SoIC service platform
With the innovative bonding scheme, TSMC-SoIC service platform enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 Âµm rule. Short die-to-die connection has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions.
Holistic 3D System Integration
TSMC-SoIC service platform integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip with a smaller footprint and thinner profile, which can be holistically integrated into advanced WLSI (aka CoWoS and InFO ). From external appearance, the newly integrated chip is just like a general SoC chip yet embedded with desired and heterogeneously integrated functionalities.
TSMC SoIC-WoW technology realize heterogeneous and homogeneous 3D silicon integration through wafer stacking process. The tight bonding pitch and thin TSV enable minimum parasitic for better performance, lower power and latency as well as smaller form factor. WoW is suitable for high yielding nodes and the same die size applications or design, it even supports integration with 3rd party wafer.